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CLC114 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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CLC114 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 10 page Typical Performance Characteristics (Continued) Application Division Operation The CLC114 is a quad, low power, high speed, unity gain buffer. The closed loop topology provides accuracy not found in open loop designs. The input stage incorporates a slew enhancement circuit which allows low quiescent power with- out sacrificing AC performance. PC Board Layout and Crosstalk High frequency devices demand a good printed circuit board layout for optimum performance. The CLC114, with power gain to 200 MHz, is no exception. A ground plane and power supply bypassing with good high frequency ceramic capaci- tors in close proximity to the supply pins is essential. Second harmonic distortion can be improved by ensuring equal cur- rent return paths for both the positive and negative supplies. This can be accomplished by grounding the bypass capaci- tors at the same point in the ground plane while keeping the power supply side of the bypass capacitors within 0.1” of the CLC114 supply pins. Crosstalk (undesired signal coupling between buffer chan- nels) is strongly dependent on board layout. Closely spaced signal traces on the circuit board will degrade crosstalk due to interface capacitance. For this reason it is recommended that unused package pins (2, 4, 6, 11) be connected to the ground plane for better channel isolation at the device pins. Similarly, crosstalk can be improved by using a grounded guard trace between signal traces. This will reduce the dis- tributed capacitance between signal lines. Following are two graphs depicting the effects of crosstalk. All-hostile crosstalk is measured by driving three of the four buffers simultaneously while observing the fourth, undriven, channel. Figure 2, “All-hostile Crosstalk Isolation”, shows this effect as a function of input signal frequency. R L is the resistive load for each driven channel. Figure 3, “Most Sus- ceptible Channel-to-Channel Pulse Coupling”, describes one effect of crosstalk when one channel is driven with a 2V PP step (tr = 5ns) while the output of the undriven channel is measured. From Figure 2 it can be observed that crosstalk decreases as the signal frequency is reduced. Similarly, the pulse coupling crosstalk will decrease as the rise time in- creases. Evaluation Board An evaluation board for the CLC114 is available. This board maybe ordered as part CLC730023. Equivalent Input Noise DS012738-16 2nd and 3rd Harmonic Distortion DS012738-17 2-Tone, 3rd Order Intermodulation Intercept DS012738-18 www.national.com 7 |
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