USB Peripheral Controller

with SPI Interface

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11

Test Circuits and Timing Diagrams

Figure 6. Rise and Fall Times

90%

10%

Figure 7. Load for D+/D- AC Measurements

MAX3420E

D+ OR D-

TEST

POINT

33

Ω

15k

Ω

SCLK

SS

MOSI

MISO

HI-Z

HI-Z

8

1

2

9

10

16

Figure 9. SPI Bus Timing Diagram (Half-Duplex Mode, SPI Mode (0,0))

SCLK

MOSI

MISO

NOTES:

1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS

FOR FULL-DUPLEX MODE.

2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.

SS

HI-Z

HI-Z

HI-Z

8

1

2

9

10

16

Figure 8. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))