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CAT25C17L-TE13 Datasheet(PDF) 3 Page - Catalyst Semiconductor |
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CAT25C17L-TE13 Datasheet(HTML) 3 Page - Catalyst Semiconductor |
3 / 12 page 3 CAT25C11/03/05/09/17 Doc. No. 1017, Rev. J Limits 1.8V-6.0V 2.5V-6.0V 4.5V-5.5V Test SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions tSU Data Setup Time 50 20 20 ns VIH = 2.4V tH Data Hold Time 50 20 20 ns CL = 100pF tWH SCK High Time 250 75 40 ns VOL = 0.8V tWL SCK Low Time 250 75 40 ns VOH = 2.0v fSCK Clock Frequency DC 1 DC 5 DC 10 MHz tLZ HOLD to Output Low Z 50 50 50 ns tRI(1) Input Rise Time 2 2 2 µs tFI(1) Input Fall Time 2 2 2 µs tHD HOLD Setup Time 100 40 40 ns tCD HOLD Hold Time 100 40 40 ns CL = 100pF tWC(3) Write Cycle Time 10 5 5 ms tV Output Valid from Clock Low 250 75 40 ns tHO Output Hold Time 0 0 0 ns tDIS Output Disable Time 250 75 75 ns tHZ HOLD to Output High Z 150 50 50 ns tCS CS High Time 500 100 100 ns tCSS CS Setup Time 500 100 100 ns tCSH CS Hold Time 500 100 100 ns tWPS WP Setup Time 150 50 50 ns tCSH CS Hold Time 150 50 50 ns (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL = 50pF (3) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. A.C. CHARACTERISTICS CL = 50pF (note 2) PIN CAPACITANCE (1) Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted). Symbol Test Conditions Max. Units Conditions COUT Output Capacitance (SO) 8 pF VOUT=0V CIN Input Capacitance ( CS, SCK, SI, WP, HOLD)6 pF VIN=0V |
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