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CS61600 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers

Part No. CS61600
Description  PCM JITTER ATTENUATOR
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gether. After the power supplies have stabilized,
and the clock has been input at CLKIN, FI-
FORST should be momentarily pulled low to re-
set the pointers of both devices. The overflow
flags should then be reset by momentarily pull-
ing RESET, pin 1, low.
Additional slaves may be added. The ARC input
may be derived from either the CLKOUT pin on
the master, or the CLKOUT pin on a preceding
slave. When using the master’s CLKOUT pin,
the fan out must be considered. Attaching several
inputs to the CLKOUT pin increases the load
that the output must drive. The added capaci-
tance will reduce the switching speed of the out-
put driver. Similarly, a configuration which uses
the CLKOUT signal of each CS61600 to drive
the subsequent CS61600 will induce some
propagation delay. These potential timing prob-
lems should be considered when cascading
CS61600s.
Maintaining Clock
Many applications require that the clock signal
from CLKOUT be maintained within some
specified range of frequencies when the clock
signal on CLKIN (often generated from a recov-
ered T1 signal clock) goes away. Figure A3
shows one method for maintaining the CLKOUT
signal. The reference clock is a locally generated
clock whose frequency lies within the tolerance
of the applicable specifications which govern the
system’s design. When the CLKIN signal goes
away, the multiplexor should switch in the refer-
ence clock. Since this clock goes through the jit-
ter attenuator, phase and frequency integrity at
CLKOUT is maintained.
Jitter Attenuation at Different Clock Rates
The CS61600 can be used to attenuate jitter at
frequencies below 2.048 MHz. For signal fre-
quencies above about 900 kHz, selection of the
appropriate crystal will suffice. For jitter attenu-
10k
V+
1
2
3
4
5
6
7
NC
NC
NC
NC
14
13
12
11
10
9
8
V+
V+
DIN 1
DIN 2
CLKIN
DOUT 2
CLKOUT
10k
V+
CS61600
MASTER
ARC
ARE
DOUT 1
OVR
RESET
OVR
RESET
200k
multiple
slaves
may be
added
NC
OVR
OVR
Q
S
R
D
Q
CLKIN
V+
10k
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CS61600
SLAVE
10k
V+
FIFO
POINTER
RESET
Figure A2. Master / Slave configuration
LOCALLY
GENERATED
REFERENCE
CLOCK
RECOVERED
CLOCK
LOSS OF
CLOCK
DETECTOR
MULTIPLEXER
CS61600
CLKIN
pin 8
1.544 MHz
1.544 MHz
CLKOUT
pin 10
Figure A3. Maintaining Clock Integrity
CS61600
DS9F3
11




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