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CS61600 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

Part No. CS61600
Description  PCM JITTER ATTENUATOR
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2.048 MHz + 50 ppm for CCITT). The crystal
oscillator must be able to reach these signal fre-
quency tolerances over the system’s operating
temperature range. The oscillator adjusts to and
holds the average frequency of the signal input
to CLKIN.
Some applications specify a narrower frequency
tolerance. In these cases, it is possible to im-
prove jitter attenuation performance by specify-
ing a crystal with less pull range. A narrow pull
range crystal has the effect of shifting the curves
shown in Figure 6 to the left. Care must be taken
to ensure that the crystal/oscillator will reach the
signal’s frequency extremes over the operating
temperature range of the system. More informa-
tion on specifying and testing crystals is pro-
vided in the Applications section at the back of
this data sheet.
FIFO Overflow/Underflow
Because the oscillator clock, which is used to
empty the FIFO, has a wider frequency range
than the standard T1 input signal, the FIFO
should never underflow or overflow. However, if
underflow or overflow occurs, the buffer
overflow/underflow flag, OVR (pin 3), goes
high. A RESET (pin 1) resets the overflow flag.
If an overflow occurs, the 16 bits of data in the
FIFO are lost. An underflow condition causes the
next 16 bits read from the FIFO to be invalid. In
either case, the CS61600 will immediately
attempt to relock on to the clock signal. Holding
RESET low disables the overflow flag, OVR.
FIFO Reset
Taking the FIFORST pin low causes most of the
subcircuits of the CS61600 to go into a reset
state. These circuits will remain in a reset
condition until FIFORST is returned to a logic 1
state. However, the outputs of the CS61600 are
undefined if FIFORST is held low for more
than 500 ms. The FIFO reset function will set
the FIFO write and read pointers to the first and
eighth locations respectively. The oscillator will
continue to run and CLKOUT will be held low.
Power-Up Reset
Upon power up, the CS61600 goes through an
in itializatio n proced ure wh ich req u ires
approximately 3 ms. During this initialization
procedure, OVR is held high. After initialization
is complete, OVR goes low. When the clock
signal is input to CLKIN, the CS61600 will
immediately try to lock onto the clock signal on
CLKIN. At this point, the FIFO may overflow,
and the RESET pin should be toggled to clear
the overflow/underflow flag, OVR.
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
Call: (512) 445-7222
CS61600
DS9F3
7




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