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CS61600 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers

Part No. CS61600
Description  PCM JITTER ATTENUATOR
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Maker  ETC1 [List of Unclassifed Manufacturers]
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Inputs
CLKIN - Clock Input, PIN 8.
Clock for the data input. This clock contains the jitter to be removed.
DIN - Data Input, PIN 13.
Input data is sampled on the falling edge of CLKIN.
ARC - Alternate Read Clock, PIN 12.
When ARE, Pin 6, is at logic 1, a clock signal on ARC will control the FIFO’s read pointer.
CLKOUT, pin 10, will be at the same frequency and phase as ARC. Setting ARE to logic 0
results in the device using its oscillator to generate CLKOUT.
Outputs
OVR - Buffer Overflow/Underflow, PIN 3.
Goes high if the FIFO overflows or underflows, and is cleared by RESET.
DOUT - Data Output, PIN 9.
Output data with jitter attenuated. DOUT is stable and valid on the rising edge of CLKOUT.
CLKOUT - Output Clock, PIN 10.
Jitter reduced clock output corresponding to the data on DOUT.
OSCOUT - Oscillator Output, Pin 11.
Output of on-chip oscillator, divided by four. This pin should be left floating for normal
operation.
CS61600
DS9F3
9




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