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CS61600-IP1 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part No. CS61600-IP1
Description  PCM JITTER ATTENUATOR
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CIRCUIT DESCRIPTION
Jitter Attenuation
The CS61600 will tolerate and attenuate at least
seven unit intervals of jitter from clock and data
signals of 1.544 MHz and 2.048 MHz. An
external clock divide circuit can be added for
jitter attenuation for lower frequency signals.
Jitter attenuation is accomplished by means of a
FIFO and a variable oscillator. The frequency of
the oscillator is controlled by logic in the
CS61600 to be the same as the average of the
input clock signal, CLKIN. Signal jitter is ab-
sorbed in the FIFO.
The FIFO’s write pointer is controlled by the
CLKIN signal. Data present on DIN is written
into the memory location selected by the write
pointer. The CLKOUT signal corresponds to the
FIFO’s read pointer and is controlled by the
crystal oscillator. Internal logic determines the
relationship of the read pointer and the write
pointer, and adjusts the speed of the oscillator.
For example, if the CLKIN signal is at a higher
frequency than the CLKOUT signal, the write
pointer will start to catch up with the read
pointer. When this situation is detected, the ca-
pacitive loading the device presents to the crystal
is reduced, resulting in an increase in oscillator
frequency and read pointer (CLKOUT) fre-
quency. The oscillator frequency is periodically
updated and adjusted to maintain the FIFO at
half full. High frequency variations in the phase
of the CLKIN signal (jitter) are absorbed in the
FIFO.
There are some advantages to this method of
jitter attenuation. The device can tolerate large
amplitude jitter at high frequencies. The device
can track slow changes of the input clock fre-
quency (wander) and tolerate input frequencies
ranging over a specified frequency tolerance.
A by product of this method of jitter attenuation
is that the greater the input jitter, the greater the
jitter attenuation, and the lower the frequency at
which the device starts to attenuate jitter.
Conversely, low amplitude jitter receives little
attenuation. This performance characteristic is
shown graphically in Figure 6.
Using the CS61600 in a Slave Configuration
It is possible to use an externally generated clock
signal to clock data out of the CS61600. When
an external clock is used, a crystal is not neces-
sary. The external clock is input to the Alternate
Read Clock input, ARC (pin 12). Holding the
Alternate Read Enable pin, ARE (pin 6), high di-
rects the CS61600 to clock data out of the FIFO
at the rate determined by ARC. Unless the clock
signal on ARC is at exactly the same average
frequency as the clock signal on CLKIN, the
CS61600 will be prone to underflow or overflow,
and data will be lost. See the Applications sec-
tion of this data sheet for more information on
the use of an alternate clock.
Oscillator and Crystal
The CS61600 requires an external 6.176000
MHz (8.192000 MHz for CCITT) crystal be
connected to pins XTALOUT and XTALIN. The
oscillator circuit divides the crystal frequency by
four, and switches various capacitive loads to
provide a clock that swings in five steps from at
le ast 1.544 MHz - 130 ppm to at least
1.544 MHz + 130 ppm (2.048 MHz - 50 ppm to
JITTER
GAIN
(dB)
0
-10
-20
-30
-40
10
100
1k
10k (Hz)
dB
5
...
UNIT INTERVALS
OF INPUT JITTER
3
1
Measurement made at 1.544 MHz
with 6.176 MHz ±200 ppm crystal.
Figure 6. Jitter Attenuation Characteristics
CS61600
6
DS9F3




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