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MediaClock™
Multimedia Clock Generator
CY24142
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07532 Rev. *B
Revised January 19, 2005
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• 3.3V operation
Benefits
• Integrated high-performance PLL eliminates the need for
— external loop filter components
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Logic Block Diagram
Pin Configuration
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
CLK1 13.5 MHz
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
CLK2 54 MHz
CLK3 18.432 MHz
16-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
OE2
XIN
XOUT
VDD
AVSS
CLK2
CLK4
CLK3
AVDD
VDDL
NC
CLK1
OE1
CLK4 18.432 MHz
VDD
VSSL
CY24142
OE2
OE1
NC
Frequency Table
Part Number Outputs
Input Frequency
Output Frequency Range
CY24142-01
4
18.432
13.5 MHz, 54 MHz, 2 x 18.432 MHz
Output Enable Options[1]
OE2
OE1
CLK1
CLK2
CLK3
CLK4
Unit
0
0
13.5
OFF
OFF
OFF
MHz
0
1
13.5
54
18.432
OFF
MHz
1
0
13.5
OFF
OFF
18.432
MHz
1
1
13.5
54
18.432
18.432
MHz
Note:
1. Output driven LOW when “OFF.”
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