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ISP1562 Datasheet(PDF) 5 Page - NXP Semiconductors |
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ISP1562 Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 98 page 9397 750 14223 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 14 July 2005 5 of 98 Philips Semiconductors ISP1562 USB PCI Host Controller 6.2 Pin description Table 2: Pin description Symbol [1] Pin Type Description GNDA 1 - analog ground AUX1V8 2 - 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 µF capacitors VI(VAUX3V3) 3 - 3.3 V auxiliary input voltage; add a 100 nF decoupling capacitor INTA# 4 I/O PCI interrupt PCI pad; 3.3 V signaling; open-drain RST# 5 I PCI reset; used to bring PCI-specific registers, sequencers and signals to a consistent state 3.3 V input pad; push-pull; CMOS GNDD 6 - digital ground PCICLK 7 I PCI system clock (33 MHz) PCI pad; 3.3 V signaling GNT# 8 I/O PCI grant; indicates to the agent that access to the bus is granted PCI pad; 3.3 V signaling REQ# 9 I/O PCI request; indicates to the arbitrator that the agent wants to use the bus PCI pad; 3.3 V signaling AD[31] 10 I/O bit 31 of multiplexed PCI address and data PCI pad; 3.3 V signaling VCC(I/O) 11 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[30] 12 I/O bit 30 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[29] 13 I/O bit 29 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[28] 14 I/O bit 28 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[27] 15 I/O bit 27 of multiplexed PCI address and data PCI pad; 3.3 V signaling VI(VREG3V3) 16 - 3.3 V regulator input voltage; add a 100 nF decoupling capacitor GNDA 17 - analog ground REG1V8 18 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 µF capacitors GNDD 19 - digital ground AD[26] 20 I/O bit 26 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[25] 21 I/O bit 25 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[24] 22 I/O bit 24 of multiplexed PCI address and data PCI pad; 3.3 V signaling |
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