M24256-BRDW6P datasheet(4/25 Pages) STMICROELECTRONICS

Part #	M24256-BRDW6P

Description	256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M24128-BW, M24128-BR, M24256-BW, M24256-BR

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SUMMARY DESCRIPTION

These I2C-compatible electrically erasable pro-

grammable memory (EEPROM) devices are orga-

nized as 32K x 8 bits (M24256-BW and M24256-

BR) and 16K x 8 bits (M24128-BW and M24128-

BR).

Figure 2. Logic Diagram

Table 2. Signal Names

I2C uses a two-wire serial interface, comprising a

bi-directional data line and a clock line. The devic-

es carry a built-in 4-bit Device Type Identifier code

(1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol,

with all memory operations synchronized by the

serial clock. Read and Write operations are initiat-

ed by a Start condition, generated by the bus mas-

ter. The Start condition is followed by a Device

Select Code and Read/Write bit (RW) (as de-

scribed in Table 3.), terminated by an acknowl-

edge bit.

When writing data to the memory, the device in-

serts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Power On Reset

In order to prevent inadvertent Write operations

during Power Up, a Power On Reset (POR) circuit

is implemented.

At Power Up, the device will not respond to any in-

struction until VCC has reached the POR threshold

voltage (this threshold is lower than the VCC mini-

mum operating voltage defined in Table 8. and Ta-

ble 9.). In the same way, as soon as VCC drops

from the normal operating voltage, below the POR

threshold voltage, all the operations are disabled

and the device will not respond to any instruction.

Prior to selecting and issuing instructions to the

memory, a valid and stable VCC voltage must be

applied. This voltage must remain stable and valid

until the end of the transmission of the instruction

and, for a Write instruction, until the completion of

the internal write cycle (tW).

Figure 3. DIP, SO and TSSOP Connections

Note: See PACKAGE MECHANICAL section for package dimen-

sions, and how to identify pin-1.

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

WC

Write Control

VCC

Supply Voltage

VSS

Ground

AI02809

SDA

VCC

M24256-B

M24128-B

WC

SCL

VSS

3

E0-E2

SDA

VSS

SCL

WC

E1

E0

VCC

E2

AI02810B

M24256-B

M24128-B

1

2

3

4

8

7

6

5

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