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DS2703 Datasheet(PDF) 10 Page - Dallas Semiconductor |
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DS2703 Datasheet(HTML) 10 Page - Dallas Semiconductor |
10 / 20 page DS2703 SHA-1 Battery Pack Authentication IC 10 of 20 Table 6. Thermistor Function Command COMMAND HEX FUNCTION Activate Thermistor A9 Activates the THM output for thermistor measurement. Activation occurs within 50 ms of command completion and continues until VB capacitor depleted. 1-Wire BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-Wire bus with multiple slaves, while a single-drop bus has only one slave device. In all instances, the DS2703 is a slave device. The bus master is typically a microprocessor in the host system. The discussion of this bus system consists of five topics: 64-bit net address, CRC generation, hardware configuration, transaction sequence, and 1-Wire signaling. 64-BIT NET ADDRESS (ROM ID) Each DS2703 has a unique, factory-programmed 1-Wire Net Address that is 64 bits in length. The term Net Address is synonymous with the ROM ID or ROM Code terms used in earlier Dallas 1-Wire product documentation. The first eight bits of the Net Address are the 1-Wire family code, (34h) for the DS2703. The next 48 bits are a unique serial number. The last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 3.). The 64-bit net address and the 1-Wire I/O circuitry built into the device enable the DS2703 to communicate through the 1-Wire protocol detailed in this data sheet. Figure 3. 1-Wire Net Address Format 8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (34H) MSb LSb CRC GENERATION The DS2703 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of the address and compare it to the 8-bit CRC from the DS2703. The host system is responsible for verifying the CRC value and taking action as a result. The DS2703 does not compare CRC values and does not prevent a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result in a communication channel with a very high level of integrity. The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as shown in Figure 4, or it can be generated in software using the polynomial X 8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products (www.maxim-ic.com/appnoteindex). In Figure 4, the Shift Register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Figure 4. 1-Wire CRC Generation Block Diagram MSb XOR XOR LSb XOR INPUT |
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