IC41C16257/IC41C16257S

IC41LV16257/IC41LV16257S

2

Integrated Circuit Solution Inc.

DR021-0A 08/11/2001

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

• Fast access and cycle time

• TTL compatible inputs and outputs

• Refresh Interval: 512 cycles/8 ms

• Refresh Mode:

RAS-Only, CAS-before-RAS

(CBR), Hidden

• Self Refresh Mode: 512 cycles/64 ms (S version

only)

• JEDEC standard pinout

• Single power supply:

— 5V ± 10% (IC41C16257)

— 3.3V ± 10% (IC41LV16257)

• Byte Write and Byte Read operation via

two

CAS

• Available in 40-pin SOJ and TSOP-2

DESCRIPTION

The

x 16-bit high-performance CMOS Dynamic Random Access

Memory. Fast Page Mode allows 512 random accesses

within a single row with access cycle time as short as 12 ns

per 16-bit word. The Byte Write control, of upper and lower

byte, makes these devices ideal for use in 16-, 32-bit wide

data bus systems.

These features make the IC41C16257 and the IC41LV16257

ideally suited for high band-width graphics, digital signal

processing, high-performance computing systems, and

peripheral applications.

The IC41C16257 and the IC41LV16257 are packaged in a

40-pin, 400mil SOJ and TSOP-2.

256K x 16 (4-MBIT) DYNAMIC RAM

WITH FAST PAGE MODE

PIN DESCRIPTIONS

A0-A8

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

UCAS

Upper Column Address

Strobe

LCAS

Lower Column Address

Strobe

Vcc

Power

GND

Ground

NC

No Connection

40-Pin SOJ

PIN CONFIGURATIONS

40-Pin TSOP-2

KEY TIMING PARAMETERS

Parameter

-35

-50

-60

Unit

Max.

50

60

ns

Max.

14

15

ns

25

30

ns

20

25

ns

60

90

110

ns