Rev. 1.2 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs

DDR2 SDRAM

IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol

Proposed Conditions

Units

Notes

IDD0

Operating one bank active-precharge current;

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA

IDD1

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =

tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern

is same as IDD4W

mA

IDD2P

Precharge power-down current;

All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

mA

IDD2Q

Precharge quiet standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

mA

IDD2N

Precharge standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

mA

IDD3P

Active power-down current;

All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0mA

mA

Slow PDN Exit MRS(12) = 1mA

mA

IDD3N

Active standby current;

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA

IDD4W

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus

inputs are SWITCHING

mA

IDD4R

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-

max(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-

ING; Data pattern is same as IDD4W

mA

IDD5B

Burst auto refresh current;

tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA

IDD6

Self refresh current;

CK and CK\ at 0V; CKE

≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Normal

mA

Low Power

mA

IDD7

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =

tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-

ing page for detailed timing conditions

mA