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UPA2753GR Datasheet(PDF) 2 Page - NEC |
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UPA2753GR Datasheet(HTML) 2 Page - NEC |
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2 / 8 page  Data Sheet G15782EJ1V0DS 2 µµµµPA2753GR ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 10 µA Gate Leakage Current IGSS VGS = ±18 V, VDS = 0 V ±10 µA Gate Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 1.5 2.0 2.5 V Forward Transfer Admittance | yfs |VDS = 10 V, ID = 4.0 A 3.0 5.5 S Drain to Source On-state Resistance RDS(on)1 VGS = 10 V, ID = 4.0 A 17.1 21.4 m Ω RDS(on)2 VGS = 4.5 V, ID = 4.0 A 23.3 31.6 m Ω RDS(on)3 VGS = 4.0 V, ID = 4.0 A 26.7 36.4 m Ω Input Capacitance Ciss VDS = 10 V 620 pF Output Capacitance Coss VGS = 0 V 160 pF Reverse Transfer Capacitance Crss f = 1 MHz 100 pF Turn-on Delay Time td(on) VDD = 15 V, ID = 4.0 A 11.2 ns Rise Time tr VGS = 10 V 7.0 ns Turn-off Delay Time td(off) RG = 10 Ω 33.0 ns Fall Time tf 6.7 ns Total Gate Charge QG VDD = 24 V 14.9 nC Gate to Source Charge QGS VGS = 10 V 2.2 nC Gate to Drain Charge QGD ID = 8.0 A 4.3 nC Body Diode Forward Voltage VF(S-D) IF = 8.0 A, VGS = 0 V 0.86 V Reverse Recovery Time trr IF = 8.0 A, VGS = 0 V 25 ns Reverse Recovery Charge Qrr di/dt = 100 A/ µs18 nC TEST CIRCUIT 3 GATE CHARGE VGS = 20 → 0 V PG. RG = 25 Ω 50 Ω D.U.T. L VDD TEST CIRCUIT 1 AVALANCHE CAPABILITY PG. D.U.T. RL VDD TEST CIRCUIT 2 SWITCHING TIME RG PG. IG = 2 mA 50 Ω D.U.T. RL VDD ID VDD IAS VDS BVDSS Starting Tch VGS 0 = 1 s Duty Cycle ≤ 1% τ µ τ VGS Wave Form VDS Wave Form VGS VDS 10% 0 0 90% 90% 90% VGS VDS ton toff td(on) tr td(off) tf 10% 10% |
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