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H27UCG8T2BTR-BC Datasheet(PDF) 38 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
38
Figure 32 : Page read
Figure 33 : Random data output
4. Device Operation
4.1. Page Read
This operation is initialized by 00h-30h to the command register along with followed by five address input cycles.
The 17,664 bytes of data within the selected page are transferred to the data registers in less than tR. The
system controller may detect the completion of this data transfer tR by analyzing the output of R/B# pin. Once
the data in a page is loaded into the data registers, they may be read out in 20掱 cycle time by sequentially
pulsing RE#. The repetitive high to low transitions of the RE# clock make the device output the data starting
from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data
output command. The column address of next data, which is going to be out, may be changed to the address,
which follows random data output command. Random data output can be operated multiple times, regardless of
how many times it is done in a page.
Random data output
Random data output operation changes the column address from which data is being read in the page register.
Random data output only is issued in Ready state. Refer to Figure 33.




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