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H27UCG8T2BTR-BC Datasheet(PDF) 42 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
42
I/Ox
90h
CLE
WE#
RE#
ADh
00h
ALE
DEh
94h
EBh
74h
44h
tWHR
Figure 37 : Read ID
4.7. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by
an address input of 00h. Six read cycles sequentially output the manufacturer code (ADh), and the device code
and 3rd, 4th, 5th, 6th cycle ID, respectively. The command register remains in Read ID mode until further
commands are issued to it. Figure 37 shows the operation sequence, while 2.10 READ ID data tables explain the
byte meaning.
Figure 39 : Multi plane read status
4.8. Read Status Register
The device contains a Status Register which may be read to find out whether read, program or erase operation is
completed, and whether the program or erase operation is completed successfully. After writing Read Status
(70h) or Multi Plane Read Status (78h,75h) command to the command register, a read cycle outputs the content
of the Status Register to the I/O pins only if CE# and RE# are low, whichever occurs last. This two line control
allows the system to poll the progress of each device in multiple memory connections even when R/B# pins are
common-wired. Refer to 2.8. STATUS REGISTER CODINGS for specific Status Register definitions and Figure 38,
Figure 39 for Read Status. The command register remains in Read Status mode until further commands are
issued to it. Therefore, if the status register is read during a random read cycle, the read command (00h) should
be given before starting read cycles.
Figure 38 : Read status




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