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H27UCG8T2BTR-BC Datasheet(PDF) 43 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
43
4.9. Page Program
The device is programmed as a page unit. The number of consecutive partial page programming operation within
the same page without an intervening erase operation must not exceed 1 times. The program addressing should
be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up
to 17,664 bytes of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell. The serial data-loading period begins by
inputting the Serial Data Input command (80h), followed by the five cycle address inputs and then serial data.
The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address of next data, which will be entered, may be changed to the address which
follows random data input command (85h). Random data input may be operated multiple times, regardless of
how many times it is done in a page. The Page Program Confirm command (10h) initiates the programming
process. Writing 10h alone without previously entering the serial data will not initiate the programming process.
The internal write state controller automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status
Register command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status
bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while
programming is in progress. The Write Status Bit (I/O 0) is valid, when all internal operations are complete
(status bit I/O 6 = high).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the
command register. Figure 40 and Figure 41 details the sequence.
Figure 40 : Page Program
Figure 41 : Random data input




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