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H27UCG8T2BTR-BC Datasheet(PDF) 44 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp

 44 page
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64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
4.10. Multi Plane Program
Device supports multiple plane program. It is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 17,664bytes of data
may be loaded into the data register, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input
command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address for this
page must be within first plane (A<23>=0). The data of first page other than those to be programmed do not
need to be loaded. The device supports random data input exactly like page program operation. The Dummy
Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time
(tDBSY). Once it has become ready again, 81h command must be issued, followed by second page address (5
cycles) and its serial data input. Address for this page must be within second plane (A<23>=1). The data of
second page other than those to be programmed do not need to be loaded. Program Confirm command (10h)
makes parallel programming of both pages start. User can check operation status by R/B# pin or read status
register command, as if it were a normal page program; status register command is also available during Dummy
Busy time (tDBSY). In case of fail in first plane or second plane page program, fail bit of status register will be set:
Pass/Fail status of each plane can be checked by Multi Plane Read Status. Figure 42 details the sequence.
Figure 42 : Multi plane page program
1. plane 0 and plane 1 should be selected within the same chip.
2. Only one block should be selected from the each plane.
3. Selected Page address except A23 within two blocks must be same.
4. Any command between 11h and 81h is prohibited except 70h/78h/75h and FFh.
5. Read Status command can be 70h or 78h or 75h.

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