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H27UCG8T2BTR-BC Datasheet(PDF) 45 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp

 45 page
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64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
4.11. Cache Program (available only within a block)
Cache Program is an extension of the standard page program, which is executed with 17,664 bytes cache
registers and same bytes data register. After the serial data input command (80h) is loaded to the command
register, followed by 5 cycles of address, a full or partial page of data is latched into the cache register, and then
the cache write command (15h) is loaded to the command register. After that sequence, the data in the cache
register is transferred into the data register for cell programming. At this time, the device remains in busy state.
After all data of the cache register is transferred into the data register, the device goes to the Ready state to
load the next data into the cache register by issuing another cache program command sequence (80h-15h).
There are some restrictions for cache program operation.
1. The cache program command is available only within a block.
2. User must give address and data after 80h command.
The Busy time of first sequence equals the time it takes to transfer the data of cache register to the data register.
Cell programming of the data of data register and loading of the next data into the cache register is consequently
processed as a pipeline method. On the second and cascading sequence, transfer from the cache register to the
data register is held off until cell programming of current data register contents has been done.
Read Status command (70h) may be issued to find out when the cache register is ready by polling the Cache-
Busy status bit (I/O 6). In addition, the status bit (I/O 5) can be used to determine when the cell programming
of the current data register contents is complete. Pass/fail status of only the previous page (I/O 1) is available
upon the return to Ready state.
If the system monitors the progress of programming only with R/B#, the last page of the target programming
sequence must be programmed with actual Page Program command (10h). If the Cache Program command (15h)
is used instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before
starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of
the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page
upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read
together when I/O 0 is checked. Refer to 2.8. Status Register Coding and Figure 43 for more details.

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