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H27UCG8T2BTR-BC Datasheet(PDF) 51 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
51
Figure 49 : Multi plane Block Erase
Figure 50 : Reset
4.16. Multi Plane Block Erase
Multiple plane erase, allows parallel erase of two blocks, one per each memory plane.
Block erase setup command (60h) must be repeated two times, each time followed by first block and second
block address respectively (3 cycles each). As for block erase, D0h command makes embedded operation start.
Multi plane erase does not need any Dummy Busy Time between first and second block address insertion.
Address limitation required for Multiple Plane Program applies also to multiple plane erase, as well as operation
progress can be checked like for Multiple Plane Program. Refer to the detail sequence as shown below.
4.17. Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy
state during random read, program or erase mode, the reset operation will abort these operations. The contents
of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The
command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when
WP# is high. Refer to 2.8. Status Register Coding for device status after reset operation. If the device is already
in reset state, the command register will not accept a new reset command. The R/B# pin goes low for tRST after
the Reset command is written. Refer to Figure 50.




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