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RT6203B Datasheet(PDF) 18 Page  Richtek Technology Corporation 

18 page RT6203B 18 DS6203B01 July 2017 www.richtek.com © Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. reduce voltage ringing and overshoot. Choose capacitors rated at higher temperatures than required. Several ceramic capacitors may be paralleled to meet the RMS current, size, and height requirements of the application. Output Capacitor Selection The RT6203B is optimized for output terminal with ceramic capacitors application and best performance will be obtained using them. The total output capacitance value is usually determined by the desired output ripple voltage level and transient response requirements for sag which is undershoot on positive load steps and soar which is overshoot on negative load steps. Output Ripple Voltage Output ripple voltage at the switching frequency is caused by the inductor current ripple and its effect on the output capacitor's ESR and stored charge. These two ripple components are called ESR ripple and capacitive ripple. Since ceramic capacitors have extremely low ESR and relatively little capacitance, both components are similar in amplitude and both should be considered if ripple is critical. RIPPLE RIPPLE(ESR) RIPPLE(C) RIPPLE(ESR) L ESR L RIPPLE(C) OUT SW V = V V V = I R I V = 8C f Output Transient Undershoot and Overshoot In addition to output ripple voltage at the switching frequency, the output capacitor and its ESR also affect the voltage sag (undershoot) and soar (overshoot) when the load steps up and down abruptly. The ACOTTM transient response is very quick and output transients are usually small. However, the combination of small ceramic output capacitors (with little capacitance), low output voltages (with little stored charge in the output capacitors), and low duty cycle applications (which require high inductance to get reasonable ripple currents with high input voltages) increases the size of voltage variations in response to very quick load changes. Typically, load changes occur slowly with respect to the IC's switching frequency. But some modern digital loads can exhibit nearly instantaneous load changes and the following section shows how to calculate the worstcase voltage swings in response to very fast load steps. The output voltage transient undershoot and overshoot each have two components : the voltage steps caused by the output capacitor's ESR, and the voltage sag and soar due to the finite output capacitance and the inductor current slew rate. Use the following formulas to check if the ESR is low enough (typically not a problem with ceramic capacitors) and the output capacitance is large enough to prevent excessive sag and soar on very fast load step edges, with the chosen inductor value. The amplitude of the ESR step up or down is a function of the load step and the ESR of the output capacitor : ESR_STEP OUT ESR V = I R The amplitude of the capacitive sag is a function of the load step, the output capacitor value, the inductor value, the inputtooutput voltage differential, and the maximum duty cycle. The maximum duty cycle during a fast transient is a function of the ontime and the minimum offtime since the ACOTTM control scheme will ramp the current using ontimes spaced apart with minimum offtimes, which is as fast as allowed. Calculate the approximate ontime (neglecting parasitic) and maximum duty cycle for a given input and output voltage as : OUT ON ON MAX IN SW ON OFF(MIN) Vt t = and D = V f t + t The actual ontime will be slightly longer as the IC compensates for voltage drops in the circuit, but we can neglect both of these since the ontime increase compensates for the voltage losses. Calculate the output voltage sag as : 2 OUT SAG OUT IN(MIN) MAX OUT L( I ) V = 2C V D V The amplitude of the capacitive soar is a function of the load step, the output capacitor value, the inductor value and the output voltage : 2 OUT SOAR OUT OUT L( I ) V = 2C V 
