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ALC888S-VD Datasheet(PDF) 29 Page - Realtek Semiconductor Corp.

Part No. ALC888S-VD
Description  7.12 CHANNEL HD AUDIO CODEC WITH TWO INDEPENDENT SPDIF OUTPUTS
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Maker  REALTEK [Realtek Semiconductor Corp.]
Homepage  https://www.realtek.com/en/
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 29 page
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ALC888S-VD
Datasheet
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
21
Track ID: JATR-2265-11
Rev. 1.2
Exit from ‘Link Reset’:
If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
SDOs
SYNC
SDIs
BCLK
Normal Frame
SYNC is absent
RST#
4 BCLK
4 BCLK
Driven Low
Driven Low
Previous Frame
Normal Frame
SYNC
Link in Reset
1
2
4
5
3
6
7
Pulled Low
Pulled Low
Driven Low
Pulled Low
Pulled Low
8
9
>=100 usec >= 4 BCLK
Initialization Sequence
Wake Event
Figure 13. Link Reset Timing
7.3.2.
Codec Reset
A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.




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