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ALC888S-VD Datasheet(PDF) 30 Page - Realtek Semiconductor Corp.

Part No. ALC888S-VD
Description  7.12 CHANNEL HD AUDIO CODEC WITH TWO INDEPENDENT SPDIF OUTPUTS
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Maker  REALTEK [Realtek Semiconductor Corp.]
Homepage  https://www.realtek.com/en/
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 30 page
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ALC888S-VD
Datasheet
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
22
Track ID: JATR-2265-11
Rev. 1.2
7.3.3.
Codec Initialization Sequence
The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
The codec will stop driving the SDI during this turnaround period
The controller drives SDI to assign a CAD to the codec
The controller releases the SDI after the CAD has been assigned
Normal operation state
SDIx
SYNC
BCLK
RST#
Connection Frame
1
2
4
5
6
7
Normal Operation
Response
Turnaround Frame
Address Frame
(Non-48kHz Frame)
Codec Drives SDIx
SD0 SD1
SD14
Controller Drives SDIx
Exit from Reset
Codec
Turnaround
( 477 BCLK
Max.)
Frame SYNC
Frame SYNC
Frame SYNC
(Non-48kHz Frame)
Controller
Turnaround
( 477 BCLK
Max.)
3
8
Codec
Drives SDIx
Figure 14. Codec Initialization Sequence
7.4. Verb and Response Format
7.4.1.
Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 8 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 9 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 8.
40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 9.
40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload




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