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ALC888S-VD Datasheet(PDF) 20 Page - Realtek Semiconductor Corp.

Part No. ALC888S-VD
Description  7.12 CHANNEL HD AUDIO CODEC WITH TWO INDEPENDENT SPDIF OUTPUTS
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Maker  REALTEK [Realtek Semiconductor Corp.]
Homepage  https://www.realtek.com/en/
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 20 page
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ALC888S-VD
Datasheet
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
12
Track ID: JATR-2265-11
Rev. 1.2
7.1.1.
Link Signal Definitions
Table 3.
Link Signal Definitions
Item
Description
BCLK
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs
SYNC
48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs
SDO
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported
SDI
Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the HDA
controller and connects to all codecs
Table 4.
HDA Signal Definitions
Signal Name
Source
Type for Controller Description
BCLK
Controller
Output
Global 24.0MHz Bit Clock
SYNC
Controller
Output
Global 48kHz Frame Sync and Outbound Tag Signal
SDO
Controller
Output
Serial Data Output from the Controller
SDI
Codec/Controller
Input/Output
Serial Data Input from Codec.
Weakly pulled down by the controller
RST#
Controller
Output
Global Active Low Reset Signal
SDO
SYNC
SDI
BCLK
Start of Frame
8-Bit Frame SYNC
7654
0
1
2
3
999 998 997 996 995 994 993 992 991 990
32
1
0
499
498
497
496
495
494
Controller samples SDI at rising edge of BCLK
Codec samples SDO at both rising and falling edge of BCLK
Figure 5.
Bit Timing




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