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AM2320 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers
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logic level "0"; during high clock line SCL and SDA data line is high logic level represents the
current transmission "1." Logic "0" (low) and "1" (high) level, is related to the level of VDD decision
(detailed in Table 3 AM2320 DC Characteristics table). In addition, each transmission of a data bit
clock pulse is generated.
Send data to the device bus
Device receiving data from the bus
Transmit clock signal generating device initialization and termination sent
The device addressed by the host
At the same time there is more than one host attempts to control the bus,
but do not destroy the message
There is a multiple hosts at the same time try to control the bus, but only
allows it a control bus and make the message is not destroyed in the
Two or more devices in the process of synchronizing the clock signal
Data line SDA data must remain stable during the high period of the clock. High or low state
of the data line SDA is only in the low period of SCL clock line only allowed to change. But at the
start and end I
C bus exceptions (for details see the start and stop conditions). Some other serial bus
data as may be required valid edge (rising or falling) of the clock signal, but I
C bus is valid level.
The specific timing diagram shown in Figure 6.
Figure 6: Bit Transfer
āStart and stop conditions
Start condition: Period when SCL is high, SDA high to low Start condition generating
transition from. Bus after the start condition is generated in a busy state. The
initial condition is often abbreviated as S.
Stop condition: Period when SCL is high, SDA generates a stop condition low to high
transition from. Bus stop condition is generated in an idle state. The stop
condition abbreviated as P.
Start and stop conditions diagram shown in Figure 7.
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