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EUP3484S Datasheet(PDF) 9 Page  Eutech Microelectronics Inc 

9 page EUP3484S DS3484S Ver1.2 May 2012 9 The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1ÂµF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple for low ESR capacitors can be estimated by: Where C1 is the input capacitance value. For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: Where C2 is the output capacitance value and RESR is the equivalent series resistance (ESR) value of the output capacitor. When using ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance which is the main cause for the output voltage ripple. For simplification, the output voltage ripple can be estimated by: When using tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: The characteristics of the output capacitor also affect the stability of the regulation system. The EUP3484S can be optimized for a wide range of capacitance and ESR values. Compensation Components EUP3484S employs current mode control for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP is the output of the internal transconductance error amplifier. A series capacitor resistor combination sets a polezero combination to govern the characteristics of the control system. The DC gain of the voltage feedback loop is given by: Where VFB is the feedback voltage (0.925V), AVEA is the error amplifier voltage gain, GCS is the current sense transconductance and RLOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3) and the output resistor of the error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located at: Where GEA is the error amplifier transconductance. The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: In this case, a third pole set by the compensation capacitor (C4) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where the feedback OUT V FB V EA V A CS G LOAD R VDC A âˆ— âˆ— âˆ— = VEA A C3 2Ï€ EA G P1 f âˆ— âˆ— = LOAD R C2 2Ï€ 1 P2 f âˆ— âˆ— = R3 C3 2Ï€ 1 Z1 f âˆ— âˆ— = ESR R C2 2 1 ESR f âˆ— âˆ— Ï€ = R3 C4 2 1 P3 f âˆ— âˆ— Ï€ = ï£· ï£· ï£¸ ï£¶ ï£¬ ï£¬ ï£ ï£« âˆ’ âˆ— âˆ— âˆ— = V IN V OUT 1 V IN V OUT S f 1 C LOAD I IN âˆ† V ï£· ï£· ï£¸ ï£¶ ï£¬ ï£¬ ï£ ï£« ï£· ï£· ï£¸ ï£¶ ï£¬ ï£¬ ï£ ï£« âˆ— âˆ— + âˆ— âˆ’ âˆ— âˆ— = C2 S f 8 1 ESR R IN V OUT V 1 L S f OUT V OUT âˆ† V ï£· ï£· ï£¸ ï£¶ ï£¬ ï£¬ ï£ ï£« âˆ’ âˆ— âˆ— âˆ— âˆ— = âˆ† IN V OUT V 1 2 C L 2 S f 8 OUT V OUT V ESR R IN V OUT V 1 L S f OUT V OUT V âˆ— âˆ’ âˆ— âˆ— = âˆ† ï£· ï£· ï£¸ ï£¶ ï£¬ ï£¬ ï£ ï£« 
