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PM25LD512 Datasheet(PDF) 19 Page - List of Unclassifed Manufacturers

Part No. PM25LD512
Description  512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus
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Maker  ETC2 [List of Unclassifed Manufacturers]
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Pm25LD512/010/ 020
Confidential information
Chingis Technology Corp.
19
DRAFT Date: August, 2010, Rev:0.4
DEVICE OPERATION (CONTINUED)
FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION
The FRDO instruction is used to read memory data on
two output pins each at up to a 100 MHz clock.
The FRDO instruction code is followed by three
address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in
during the rising edge of SCK. Then the first data byte
addressed is shifted out on the SO and SIO lines, with
each pair of bits shifted out at a maximum frequency
fCT, during the falling edge of SCK. The first bit (MSb)
is output on SO, while simultaneously the second bit is
output on SIO.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDO instruction. FRDO instruction
is terminated by driving CE# high (VIH).
Figure 14. Fast Read Dual-Output Sequence
0
1
2
3
4
5
6
7
8
9
10
11
28
29
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31
...
INSTRUCTION = 0011 1011b
...
23
22
21
3
2
1
0
3 - BYTE ADDRESS
CE#
SCK
SIO
SO
HIGH IMPEDANCE
32
33
34
35
36
37
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39
40
41
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48
7
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3
2
1
0
7
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3
2
1
0
7
6
CE#
SCK
SIO
SO
HIGH IMPEDANCE
DATA OUT 1
DATA OUT 2




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