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Pm25LD512-KCE Datasheet(PDF) 27 Page - List of Unclassifed Manufacturers |
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Pm25LD512-KCE Datasheet(HTML) 27 Page - List of Unclassifed Manufacturers |
27 / 33 page Pm25LD512/010/ 020 Confidential information Chingis Technology Corp. 27 DRAFT Date: August, 2010, Rev:0.4 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (CE# must follow the voltage applied on Vcc) until Vcc reaches the correct value: - Vcc(min) at Power-up, and then for a further delay of tVCE - Vss at Power-down Usually a simple pull-up resistor on CE# can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while Vcc is less than the POR threshold value (Vwi) during power up, the device does not respond to any instruction until a time delay of tPUW has elapsed after the moment that Vcc rised above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No Write Status Register, Program or Erase instructions should be sent until the later of: - tPUW after Vcc passed the VWI threshold - tVCE after Vcc passed the Vcc(min) level At Power-up, the device is in the following state: - The device is in the Standby mode - The Write Enable Latch (WEL) bit is reset At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. Chip Selection Not Allowed All Write Commands are Rejected tVCE Read Access Allowed Device fully accessible tPUW Vcc Vcc(max) Vcc(min) Reset State V (write inhibit) Time Symbol Parameter Min. Max. Unit tVCE *1 Vcc(min) to CE# Low 10 us tPUW *1 Power-Up time delay to Write instruction 1 10 ms VWI *1 Write Inhibit Voltage 2.1 V Note : *1. These parameters are characterized only. 1.8 1.6 |
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