HY57V281620ET datasheet(11/13 Pages) HYNIX

Part #	HY57V281620ET

Description	128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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11 / 13 page

Rev. 1.1 / Jan. 2005

11

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY57V281620E(L)T(P) Series

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

Note: 1. A new command can be given tRRC after self refresh exit.

Parameter

Symbol

5

6

7

H

Unit Note

Min Max Min Max Min Max Min Max

RAS Cycle Time

Operation

tRC

55

-

60

-

63

-

63

-

ns

RAS Cycle Time

Auto Refresh

tRRC

55

-

60

-

63

-

63

-

ns

RAS to CAS Delay

tRCD

15

-

18

-

20

-

20

-

ns

RAS Active Time

tRAS

38.7 100K

42

100K

42

100K

42 120K ns

RAS Precharge Time

tRP

15

-

18

-

20

-

20

-

ns

RAS to RAS Bank Active Delay

tRRD

10

-

12

-

14

-

15

-

ns

CAS to CAS Delay

tCCD

1-1-1-

1

-

CLK

Write Command to

Data-In Delay

tWTL

0

-0

-

0

-

CLK

Data-in to Precharge Command

tDPL

2-2-2-

2

-

CLK

Data-In to Active Command

tDAL

tDPL + tRP

DQM to Data-Out Hi-Z

tDQZ

2-2-2-

2

-

CLK

DQM to Data-In Mask

tDQM

0-0-0-

0

-

CLK

MRS to New Command

tMRD

2-2-2-

2

-

CLK

Precharge to Data

Output High-Z

CAS

Latency=3

tPROZ3

3-3-3-

3

-

CLK

CAS

Latency=2

tPROZ2

2-2-2-

2

-

CLK

Power Down Exit Time

tDPE

1-1-1-

1

-

CLK

Self Refresh Exit Time

tSRE

1-1-1-

1

-

CLK

1

Refresh Time

tREF

-64-64

-64

-

64

ms

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