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LM5026MT Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LM5026MT Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 23 page  Detailed Operating Description The LM5026 PWM controller contains all of the features necessary to implement power converters utilizing the active clamp reset technique with current mode control. With the active clamp reset, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp reset techniques. The LM5026 pro- vides two control outputs, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The device can be configured to drive either a P-Channel or N-Channel clamp switch. The main switch gate driver fea- tures a compound configuration consisting of both MOS and bipolar devices, which provide superior gate drive character- istics. The LM5026 can be configured to operate with bias voltages over a wide input range from 8V to 100V. Additional features include programmable maximum duty cycle, line under-voltage lockout, cycle-by-cycle current limit, hiccup mode fault protection with adjustable delays, PWM slope compensation, soft-start, a 1MHz capable oscillator with syn- chronization Input / Output capability, precision reference and thermal shutdown. High Voltage Start-Up Regulator The LM5026 contains an internal high voltage start-up regu- lator that allows the input pin (VIN) to be connected directly to a nominal 48V dc line voltage. The regulator output (VCC) is internally current limited to 20mA. When power is applied and the UVLO pin potential is greater than 0.4V, the regula- tor is enabled and sources current into an external capacitor connected to the VCC pin. The recommended capacitance range for the VCC regulator is 0.1µF to 100µF. The VCC regulator provides power to the internal voltage reference, PWM controller and gate drivers. The controller outputs are enabled when the voltage on the VCC pin reaches the regulation point of 7.6V, the internal voltage reference (REF) reaches its regulation point of 5V and the UVLO voltage is greater than 1.25V. In typical applications, an auxiliary trans- former winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8V to shut off the internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the con- troller’s power dissipation. The external VCC capacitor must be sized such that the current delivered from the capacitor and the VCC regulator will maintain a VCC voltage greater than 6.2V during the initial start-up. During a fault mode when the converter aux- iliary winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the IC package. An external start-up or bias regulator can be used to power the LM5026 instead of the internal start-up regulator by connecting the VCC and the VIN pins together and connecting an external bias supply to these two pins. Line Under-Voltage Detector The LM5026 contains a dual level Under-Voltage Lockout (UVLO) circuit. When the UVLO pin voltage is below 0.4V the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4V but less than 1.25V, the controller is in standby mode. In standby mode the VCC and REF bias regulators are active while the controller out- puts are disabled. When the VCC and REF outputs exceed the VCC and REF under-voltage thresholds and the UVLO pin voltage is greater than 1.25V, the outputs are enabled and normal operation begins. An external set-point voltage divider from VIN to GND can be used to set the operational range of the converter. The divider must be designed such that the voltage at the UVLO pin will be greater than 1.25V when VIN is in the desired operating range. UVLO hysteresis is accomplished with an internal 20uA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold, the current source is turned off causing the voltage at the UVLO pin to fall. The hysteresis of the 0.4V shutdown com- parator is fixed at 100mV. The UVLO pin can also be used to implement various re- mote enable / disable functions. Pulling the UVLO pin below the 0.4V threshold totally disables the controller. Pulling the UVLO pin to a potential between 1.25 and 0.4V places the controller in standby with the VCC and REF regulators op- erating. Turning off a converter by forcing the UVLO pin to the standby condition provides a controlled soft-stop. The controller outputs are not directly disabled in standby mode, rather the soft-start capacitor is discharged with a 50µA sink current. Discharging the soft-start capacitor gradually re- duces the PWM duty cycle to zero, providing a slow con- trolled discharge of the power converter output filter. This controlled discharge can help prevent uncontrolled behavior of self-driven synchronous rectifiers during turn-off. PWM Outputs The relative phase of the main switch gate driver OUT_A and active clamp gate driver OUT_B can be configured for mul- tiple applications. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two outputs should be in phase, with the active clamp output overlapping the main output. For active clamp configurations utilizing a high side N-Channel switch, the active clamp output should be out of phase with main output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the LM5026 is the ability to accurately configure either deadtime (both off) or overlap time (both on) of the gate driver outputs. The overlap / deadtime magnitude is controlled by the resistor value (RSET) connected to the TIME pin of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or to AGND for overlap control. The internal configuration detector senses the direction of current flow in the TIME pin resistor and configures the phase relationship of the main and active clamp outputs. www.national.com 11 |
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