©2004 Fairchild Semiconductor Corporation

RMBA19500A Rev. C

Application Information

CAUTION: THIS IS AN ESD SENSITIVE DEVICE

The following describes a procedure for evaluating the RMBA19500A, a monolithic high efficiency power amplifier, in a

surface mount package, designed for use as a driver stage for PCS1900 Base station or as the final output stage for Micro-

and Pico-Cell base stations. Figure 1 shows the package outline and the pin designations. Figure 2 shows the functional

block diagram of the packaged product. The RMBA19500A requires external passive components for DC bias and RF input

and output matching circuits as shown in Figure 3 and the Parts List. A recommended schematic circuit is shown in Figure

3. The gate biases for the three stages of the amplifier may be set by simple resistive voltage dividers. Figure 4 shows a

typical layout of an evaluation board, corresponding to the schematic circuits of Figure 3. The following designations should

be noted:

(1) Pin designations are as shown in Figure 2.

(2) Vg1, Vg2, and Vg3 are the Gate Voltages (negative) applied at the pins of the package.

(3) Vgg1, 2, and Vgg3 are the negative supply voltages at the evaluation board terminals (Vg1 and Vg2 are tied together).

(4) Vd1, Vd2, and Vd3 are the Drain Voltages (positive) applied at the pins of the package.

(5) Vdd is the positive supply voltage at the evaluation board terminal (Vd1, Vd2, and Vd3 are tied together).

Note: The base of the package must be soldered on to a heat sink for proper operation.

Figure 1. Package Outline and Pin Designations

65

0.200 SQ.

0.011

RMBA19500A

0.030

0.020

0.015

4

45

Bottom View

Top View

Plastic Lid

Side Section

6

12 11 10

7

8

9

3

2

1

10

3

2

1

7

8

9

11 12

0.041

0.075 MAX

0.010

Dimensions in inches

0.282

0.246

0.230

Pin

Description

1

RF Out & Vd3

2

RF Out & Vd3

3

RF Out & Vd3

4

VD1

5

GND

6

VG1

7

RF In

8

GND

9

VG2

10

VD2

11

GND

12

VG3

13

GND