VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8116

ATM/SONET/SDH 622/155Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

G52220-0, Rev 4.1

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

1/8/00

Table 3: Clock Multiplier Unit Performance

(1)

These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements

(< 10 mUIrms)

(2)

Needed to meet SONET output frequency stability requirements

(3)

Measured

Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.

AC Timing Characteristics

Figure 7: Receive High Speed Data Input Timing Diagram

Table 4: Receive High Speed Data Input Timing Table

(STS-12 Operation)

Name

Description

Min

Typ

Max

Units

RCd

Reference clock duty cycle

40

60

%

RCj

13

ps

RCj

5ps

-20

+20

ppm

OCj

8ps

OCj

15

ps

OCfrange

Output frequency

620

624

MHz

OCd

Output clock duty cycle

40

60

%

Parameter

Description

Min

Typ

Max

Units

Receive clock period

-

1.608

-

ns

Serial data setup time with respect to RXCLKIN

250

-

-

ps

Serial data hold time with respect to RXCLKIN

250

-

-

ps

RXCLKIN+

RXCLKIN-

RXDATAIN+

RXDATAIN-