CY7C1327F
Document #: 38-05216 Rev. *B
Page 4 of 17
Pin Definitions
Name
TQFP
BGA
I/O
Description
A0, A1, A
37,36,
32,33,34,
35,44,45,
46,47,48,
49,50,80,
81,82,99,
100
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,
C6,R6,T6
Input-
Synchronous
Address Inputs used to select one of the 256K address locations. Sampled
at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1,
CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter.
BWA,BWB
93,94
L5,G3
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct
byte writes to the SRAM. Sampled on the rising edge of CLK.
GW
88
H4
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the
rising edge of CLK, a global write is conducted (ALL bytes are written,
regardless of the values on BW[A:B] and BWE).
BWE
87
M4
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of
CLK. This signal must be asserted LOW to conduct a byte write.
CLK
89
K4
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
CE1
98
E4
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP
is ignored if CE1 is HIGH.
CE2
97
B2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Used in conjunction with CE1 and CE3 to select/deselect the device.
CE3
92
B6
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE1 and CE2 to select/deselect the device. Not
connected for BGA. Where referenced, CE3 is assumed active throughout
this document for BGA.
OE
86
F4
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE is masked during the first clock of a read cycle when emerging from a
deselected state.
ADV
83
G4
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active
LOW. When asserted, it automatically increments the address in a burst
cycle.
ADSP
84
A4
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK,
active LOW. When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
ZZ
64
T7
Input-
Asynchronous
ZZ “sleep” Input, active HIGH. This input, when High places the device
in a non-time-critical “sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
ADSC
85
B4
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK,
active LOW. When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
DQA,
DQB
DQPA,
DQPB
58,59,62,
63,68,69,
72,73
8,9,12,13,
18,19,22,
23
74,24
F6,H6,L6,
N6,E7,G7,
K7,P7
D1,H1,L1,
N1,E2,G2,
K2,M2,
D6,P2
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they deliver
the data contained in the memory location specified by “A” during the
previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs and DQP[A:B] are placed in a three-state condition.
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