8 / 13 page
PRELIMINARY
CY7C1352G
Document #: 38-05514 Rev. *A
Page 8 of 13
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected,
or VIN ≤ 0.3V or VIN > VDDQ –
0.3V
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
105
mA
5-ns cycle, 200 MHz
95
mA
6-ns cycle, 166 MHz
85
mA
7.5-ns cycle, 133
MHz
75
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speeds
45
mA
Thermal Resistance[11]
Parameter
Description
Test Conditions
TQFP Package
Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
TBD
°C/W
Θ
JC
Thermal Resistance
(Junction to Case)
TBD
°C/W
Capacitance[11]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
5pF
CCLK
Clock Input Capacitance
5
pF
CI/O
Input/Output Capacitance
5
pF
AC Test Loads and Waveforms
Note:
11. Tested initially and after any design or process changes that may affect these parameters.
Electrical Characteristics Over the Operating Range [9, 10] (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
1ns
OUTPUT
R = 317
Ω
R = 351
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.5V
3.3V
ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
OUTPUT
R = 1667
Ω
R =1538
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.25V
2.5V
ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
