MAX1438 datasheet(5/23 Pages) MAXIM

Part #	MAX1438

Description	Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

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5 / 23 page

Octal, 12-Bit, 50Msps, 1.8V ADC

with Serial LVDS Outputs

_______________________________________________________________________________________

5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1µF, CREFP to GND = 10µF,

CREFN to GND = 10µF, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at

TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (Note 6)

Data Valid to CLKOUT Rise/Fall

tOD

Figure 5 (Note 7)

(tSAMPLE /

24)

- 0.15

(tSAMPLE /

24)

+ 0.15

ns

CLKOUT Output-Width High

tCH

Figure 5

tSAMPLE /

12

ns

CLKOUT Output-Width Low

tCL

Figure 5

tSAMPLE /

12

ns

FRAME Rise to CLKOUT Rise

tCF

Figure 4 (Note 7)

(tSAMPLE /

24)

- 0.15

(tSAMPLE /

24)

+ 0.15

ns

Sample CLK Rise to FRAME Rise

tSF

Figure 4 (Note 7)

(tSAMPLE /

2)

+ 1.1

(tSAMPLE /

2)

+ 2.6

ns

Crosstalk

(Note 2)

-95

dB

Gain Matching

CGM

fIN = 5.3MHz (Note 2)

±0.1

dB

Phase Matching

CPM

fIN = 5.3MHz (Note 2)

±0.25

Degrees

Note 1: Specifications at TA

≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design

and characterization and not subject to production testing.

Note 2: See definition in the Parameter Definition section at the end of this data sheet.

Note 3: See the Common-Mode Output (CMOUT) section.

Note 4: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal

bandgap reference and enable external reference mode.

Note 5: Measured using CREFP to GND = 1µF and CREFN to GND = 1µF. tENABLE time may be lowered by using smaller capacitor values.

Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.

Note 7: Guaranteed by design and characterization. Not subject to production testing.

Typical Operating Characteristics

(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz

(50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)

FFT PLOT

(16,384-POINT DATA RECORD)

FREQUENCY (MHz)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-90

-110

510

15

020

25

HD2

HD3

fCLK = 50.1523789MHz

fIN = 5.304814MHz

AIN = -0.5dBFS

SNR = 69.959dB

SINAD = 69.950dB

THD = -96.635dBc

SFDR = 96.503dBc

FFT PLOT

(16,384-POINT DATA RECORD)

FREQUENCY (MHz)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-90

-110

fCLK = 50.1523789MHz

fIN = 24.0997118MHz

AIN = -0.5dBFS

SNR = 69.707dB

SINAD = 69.672dB

THD = -90.672dBc

SFDR = 93.694dBc

510

15

020

25

HD2

HD3

CROSSTALK

(16,384-POINT DATA RECORD)

FREQUENCY (MHz)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-110

-90

MEASURED ON CHANNEL 1,

WITH INTERFERING SIGNAL

ON CHANNEL 2

fIN(IN1) = 5.304814MHz

fIN(IN2) = 24.0997118MHz

CROSSTALK = 103dB

510

15

020

25

fIN(IN2)

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