¡ Semiconductor

MSM7704-01/02/03

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DOUT2

PCM signal output for channel 2 when the parallel mode is selected.

The PCM output signal is output from MSD in a sequential order, at the rising edge of the BCLK

signal.

MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK

and XSYNC.

This pin is in a high impedance state except during 8-bit PCM output. It is also in a high

impedance state during power-saving state or power-down state.

When the serial mode is selected, this pin is left open.

A pull-up resistor must be connected to this pin because it is an open drain output.

This device is compatible with the ITU-T recommendation on coding law and output coding

format.

The MSM7704-03 (A-law) outputs the character signal inverting the even bits.

CHPS

Control signal input for the mode selection of PCM input and output.

When this signal is at a logic "1" level, the PCM input and output are in the parallel mode. The

PCM data of CH1 and CH2 is input to DIN1 and DIN2 and output from DOUT1 and DOUT2 with

the same timing.

When this signal is at a logic "0" level, the PCM input and output are in the serial mode. The PCM

data of CH1 and CH2 is input to DIN2 and output from DOUT1 as time division multiplexed

data.

The parallel mode is conveniently applied to the digital interface to the echo canceller device, and

the serial mode is applied to the digital interface to PCM multiplexer's for PABXs.

PDN

Power down control signal.

When PDN is at a logic "0" level, both transmit and receive circuits are in power down state.

AG

Analog signal ground.

DG

Ground for the digital signal circuits.

This ground is separate from the analog signal ground. The DG pin must be connected to the AG

pin on the printed circuit board to make a common analog ground.