TMS38054

RING INTERFACE DEVICE

SPWS008C – APRIL 1991 – REVISED MAY 1997

7

POST OFFICE BOX 655303

watchdog timer

The watchdog timer provides protection against a failed adapter remaining on the ring. NSRT must be toggled

low or the watchdog timer turns off the phantom drive. The period of the watchdog timer is determined by the

value of the external capacitor connected to WDTCAP. The capacitor is chosen to give a period of 21 ms

minimum and 50 ms maximum. This assures compatibility with a system that toggles NSRT at a rate faster than

once every 20 ms and assures deinsertion from the ring within 50 ms of the last NSRT high-to-low transition.

The duty cycle of NSRT is not critical. Phantom drive is turned on following a falling NSRT edge. Deinsertion

occurs if NSRT is left high or low or if the internal-wrap mode is selected from WRAP. The following describes

the operation of the watchdog timer and indicates the priorities of the control signals:

–

Phantom drive is off. Operation of the watchdog timer is not defined but can continue, and if the timer

has not expired, taking WRAP high can result in the phantom drive being turned on.

–

If the timing capacitor is connected and NSRT goes from high to low, the timing capacitor is charged or

recharged to a defined level. Phantom drive is on and discharging of the timing capacitor continues.

–

If the timing capacitor is connected and NSRT goes from low to high, there is no effect on the watchdog

timer and the discharging of the timing capacitor continues.

–

If the timing capacitor is connected and the capacitor discharges to a defined level, the phantom drive is

turned off regardless of the state of WRAP.

–

drive is controlled directly by NSRT. This serves to disable the watchdog-timer function.

voltage regulator

The internal voltage regulator is used to make the performance of the TMS38054 less dependent on the supply

voltage. The regulator consists of a band-gap reference scaled up to a nominal 3.9 V with a temperature

coefficient designed to compensate for coefficients in circuits referenced to the voltage regulator.

PLL/clock recovery

The TMS38054 contains a PLL for recovering a data clock from the received bit stream. The elements of PLL

are: phase and frequency detectors, a charge pump, an external filter (connected to FILTER), a filter buffer, a

voltage-to-current converter, and a voltage-controlled oscillator (VCO). There are three pins on the TMS38054

that allow connection to external components and tuning of the characteristics of the PLL. These pins are

FILTER, STERES, and VCOGAN. Figure 2 illustrates these blocks. The following paragraphs describe the PLL

elements.