TMS38054

RING INTERFACE DEVICE

SPWS008C – APRIL 1991 – REVISED MAY 1997

10

POST OFFICE BOX 655303

external filter (continued)

The simplified equations for the PLL are:

VCO gain

+ (G

p)(F)

rad/(s

• v)

(1)

Phase-detector gain

K

d

+

G

3

2

p

A/rad

PLL-noise-equivalent bandwidth

B

L

+

4

Hz

Where:

F

= the frequency divider factor; i.e., F = 1 for 16-Mbps operation

F = 0.25 for 4-Mbps operation

These equations are only a guide and the actual bandwidth and PLL-damping characteristics should be

obtained through correlation and modeling on specific hardware implementations that take into effect all circuit

card parasitics. Both 16-Mbps and 4-Mbps ring operation can be achieved by suitable selection of glue

components at each frequency. More information on PLL characteristics are found in:

pp. 1849–1858, Nov. 1980

.

filter buffer and voltage-to-current converter (V/I)

The filter-buffer amplifier is a unity-gain amplifier used to buffer the voltage present at FILTER with minimal

leakage current. The output of the filter buffer drives a voltage-current (V/I) converter that produces equal

currents, proportional to the filter voltage, for use in the VCO. The current level or constant of proportionality

is set by the external resistor connected to ground connected at VCOGAN. This resistor sets the VCO gain,

which is critical to loop gain and damping. The filter voltage range over which the current level tracks the voltage

determines the pull-in range of the VCO.

VCO

The VCO is an emitter-coupled astable multivibrator. The frequency is set by internal circuit parameters, the

currents from the filter buffer, and an internal VCO timing capacitor. Symmetrical circuit design helps ensure

symmetry of the VCO output, which has a nominal frequency of 32 MHz. The VCO output is buffered and sent

to the divider (for 4-Mbps operation) and multiplexer circuit.

divider and multiplexer

The multiplexer selects the source of the recovered clock, which can be either the direct output of the VCO

(nominally a 32-MHz signal) or the divided version of the VCO output (nominally an 8-MHz signal) for 16- or

4-Mbps operation. The output clock of the VCO is fed to a divide-by-4 circuit and to a multiplexer. The divider

is enabled when SPSW is high. The recovered clock is passed to frequency and phase detectors, the clock of

the data latch, and is buffered at RCLK and passed on to the ’380C2x commprocessor for processing of the

received data.