TPS51020

SLUS564B − JULY 2003 − REVISED DECEMBER 2003

4

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ELECTRICAL CHARACTERISTICS (continued)

TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,

INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =

OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)

PARAMETER

UNIT

MAX

TYP

MIN

TEST CONDITIONS

REF_X REFERENCE VOLTAGE

VREF10

10-V reference voltage

VIN = 14 V,

IOUT = 0 A

8.5

10.0

11.0

V

VLD10

Load regulation

0 mA

≤ IOUT ≤ 2 mA,

VIN = 18 V

-12%

-20%

VLN10

Line regulation

IOUT = 100 µA,

14 V

≤VIN ≤28 V

5%

VREFVTT

VTT reference voltage

DDR = 0 V wrt VO1_VDDQ input divided by 2

VVO1 = 2.5 V

1.5%

VREFVTT

VTT reference load regulation

0 mA

≤ IO ≤ 3 mA

0.75%

POWERGOOD COMPARATORS

VTHDUAL(PG) PGOOD threshold (dual mode)

Undervoltage PGOOD

765

786

808

mV

VTHDUAL(PG) PGOOD threshold (dual mode)

Overvoltage PGOOD

892

920

945

mV

VTHDDR(PG) PGOOD threshold (DDR)

Undervoltage PGOOD,

VO1_VDDQ = 2.5 V

1.12

1.14

1.16

V

VTHDDR(PG) PGOOD threshold (DDR)

Overvoltage PGOOD,

VO1_VDDQ = 2.5 V

1.28

1.31

1.33

V

TPG(del)

PGOOD delay time

INVx > undervoltage PGOOD,

Delay time from SSTRTx > 1.5 V to PGOOD

going high

2048

clks

DIGITAL CONTROL INPUTS

VIH

High-level input voltage, logic

DDR, ENBL1, ENBL2, SKIP

2.2

V

VIL

Low-level input voltage, logic

DDR, ENBL1, ENBL2, SKIP

0.3

V

IINLEAK

Logic input leakage current

DDR, ENBL1, ENBL2, SKIP= 5 V

|1.0|

µA

VO1_VDDQ and VO2

RVOUT

VOx sink impedance

VVOUTx = 0.5 V,

fault engaged

6

10

Ω

VVOUTOK

VOx low restart voltage

Fault condition removed, restart

0.25

0.32

0.40

V

VVO2LEAK

VOx input leakage current

DDR= VIN,

VOx = 5 V

|1.0|

µA

RVOUT

VO1_VDDQ input impedance

DDR= 0

1.5

M

Ω

UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

VOVPDUAL

OVP trip output threshold (dual)

Sensed at INVx

945

970

1010

mV

VOVPDDR

OVP trip output threshold (DDR)

VO1_VDDQ = 2.5 V

1.31

1.36

1.41

V

TOVP(del)

OVP propagation delay time(1)

20

µs

VUVPDUAL

UVP trip output threshold (dual)

Sensed at INVx

510

553

595

mV

VUVPDDR

UVP trip output threshold (DDR)

VO1_VDDQ = 2.5 V

750

813

875

mV

TUVP(del)

UVP propagation delay time

4096

clks

OVERCURRENT and INPUT VOLTAGE UVLO PROTECTION

ITRIPSNK

TRIPx sink current

VTRIPx = VIN − 100 mV,

TA = 25°C

11

13

15

A

ITRIPSRC

TRIPx source current

VTRIPx = 100 mV,

TA = 25°C

10

13

16

µA

TCITRIP

TRIP current temperature coeficient(1)

TA = 25°C

4200

ppm/

°C

VOCPHI

High-level OCP comparator offset voltage(1)

0

|3.0|

mV

VOCPLO

Low-level OCP comparator offset voltage(1)

0

|5.0|

mV

VVINUVLO

VIN UVLO trip threshold

REF5V_IN = 4.8 V

3.7

3.9

4.1

V

VVINHYS

VIN UVLO trip hysteresis

100

200

300

mV