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TPS77415DGK Datasheet(PDF) 5 Page - Texas Instruments |
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TPS77415DGK Datasheet(HTML) 5 Page - Texas Instruments |
5 / 24 page TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS774xx PG timing diagram † Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VI Vres† t t t VO Threshold Voltage PG Output Output Undefined Output Undefined VIT +‡ VIT –‡ VIT –‡ VIT +‡ ‡ VIT – Trip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage. Vres† |
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