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SN74LV8151DW Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LV8151DW Datasheet(HTML) 1 Page - Texas Instruments |
1 / 14 page SN74LV8151 10BIT UNIVERSAL SCHMITT TRIGGER BUFFER WITH 3STATE OUTPUTS SCES610 − OCTOBER 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 2-V to 5.5-V VCC Operation D Max tpd of 15 ns at 5 V D Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time D Polarity Control for Y Outputs Selects True or Complementary Logic D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Supports Mixed-Mode Voltage Operation on All Ports D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V VCC operation. The logic control (T/C) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C is high, the Y outputs are noninverted (true logic ), and when T/C is low, the Y outputs are inverted (complementary logic). When output-enable (OE) input is low, the device passes data from Dn to Yn. When OE is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − NT Tube SN74LV8151NT SN74LV8151NT −40 °C to 85°C TSSOP − PW Tube SN74LV8151PW LV8151 −40 C to 85 C TSSOP − PW Tape and reel SN74LV8151PWR LV8151 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. NT OR PW PACKAGE (TOP VIEW) T/C A B D1 D2 D3 D4 D5 D6 D7 D8 GND VCC P N Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 OE 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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