3D PLUS S.A. reserves the right to change or cancel products or specifications without notice
3DFP-0014-REV : 4 - SEPT. 2003
MEMORY MODULE
SDRam 128Mx16-SOP
Synchronous Dynamic Ram
MODULE
MMSD16128808S-V
2Gbit SDRam organized as 128Mx16, based on 32Mx8
ULYSSE
(3DSD2048-163)
Pin Assignment (Top View)
SOP 58 - (Pitch : 0.80 mm)
Features
General description
SDRam Memory Module
The MMSD16128808S-V is a high-speed highly integrated
Synchronous Dynamic Random Access Memory containing
2,147,483,648 bits.
It is organized with four banks of 512 Mbit.
Each bank has a 16-bit interface and is selected with specific #CS
CLK and CKE.
It is particularly well suited for use in high reliability, high
performance and high density system applications, such as
solid state mass recorder, server or workstation.
The MMSD16128808S-V is
packaged in a 58 pin SOP.
1
3
2
4
6
8
Bank 0, #CS0
DQ0-DQ7
Bank 2, #CS2
Bank 3, #CS3
DQM0
DQ8-DQ15
DQM1
7
5
Bank 1, #CS1
CLK0, CKE0
CLK1, CKE1
CLK0, CKE0
CLK1, CKE1
VDDQ
DQ8
DQ1
VSSQ
DQ9
DQ2
VDDQ
DQ10
DQ3
DQ11
VDD
#CS1
#WE
#CAS
#RAS
VSSQ
VDD
DQ0
A0
A1
A2
A3
#CS3
CLK1
CKE1
A5
A6
A7
A8
VSS
BA1
A10/AP
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
21
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
VSS
DQ15
VDDQ
DQ4
DQ14
VSSQ
DQ5
VDDQ
DQ6
DQ7
VSS
DQ13
CKE0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
A4
VSSQ
DQ12
DQM0
CLK0
19
37
20
38
#CS0
BA0
39
40
55
56
57
58
A9
A11
A12
DQM1
VDD
#CS2
- Stack of eight 256Mbit SDRam.
- Organized as 128Mx16-bit.
- Single +3.3V ±0.3V power supply.
- Fully synchronous ; all signals registered on positive edge of
system clock.
- Internal pipelined operation ; column adress can be changed
every clock cycle.
- Programmable burst lengths ; 1, 2, 4, 8 or full page.
- Auto Precharge, includes Concurrent Auto Precharge, and
Auto Refresh Modes.
- Self Refresh Modes.
- LVTTL-compatible inputs and outputs.
- Available Temperature Range :
0°C to +70°C
-40°C to +85°C
- Available with screening option for high reliability application
(Space, etc...).
(All others signals are common to the eight memories)
FUNCTIONAL BLOCK DIAGRAM
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