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MSM9000B-XX Datasheet(PDF) 7 Page - OKI electronic componets |
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MSM9000B-XX Datasheet(HTML) 7 Page - OKI electronic componets |
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7 / 38 page  ¡ Semiconductor 7/38 MSM9000B-xx DC Characteristics (2) Parameter Symbol Condition Min. Typ. Max. Unit Bias voltage 1 –VSS1 –VSS2, 3 = "A"V 1/2A–0.1 1/2A 1/2A+0.1 V –VSS5 –VSS2, 3 = "A"V 2A–0.2 2A 2A+0.2 –Vcon VBI for each stage 0.18 0.21 0.26 (VDD=0 V, VSS=–3 V, Ta=–30 to +85°C) Bias voltage 5 Contrast pitch V V Applicable pin VSS1 VSS5 — Bias voltages 2 and 3 –VSS2,3 N1 = "L", N2 = "L" Contrast = "5" 1.9 2.2 2.5 V VSS2, 3 Bias voltage 4 –VSS4 –VSS2, 3 = "A"V 3/2A–0.1 3/2A 3/2A+0.1 V VSS4 Note 1: Connect a 0.1 µF capacitor to the LCD bias generator. Note 2: The values in this table are assured when the chip is not exposed to light. AC Characteristics Parallel interface Note: The values in this table are assured when the chip is not exposed to light. Parameter Symbol Condition Min. RD high-level width tWRH — RD low-level width tWRL 200 WR high-level width tWWH WR low-level width — tWWL 200 — 200 — 200 Max. — — — — Unit ns ns ns ns WR-RD high-level width — tWWRH 200 — ns CS or C/D setup time — tAS 50 — ns CS or C/D hold time — tAH 0— ns Write data setup time — tDSW 50 — ns Write data hold time — tDHW 50 — ns Read data output delay time CL=50 pF tDDR — 200 ns Read data hold time — tDHR 20 — ns External clock high-level width — tWCH 1— ms External clock low-level width — tWCL 1— ms RESET pulse width — tWRE 2.0 — ms Rise and fall time of external clock — tr, tf — 100 ns (VDD=2.5 to 3.3 V, VBI=3 to 5.5 V, Ta=–30 to +85°C) |
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Similar Description - MSM9000B-XX |
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