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CD4070B Datasheet(PDF) 1 Page - Silicon Supplies

Part No. CD4070B
Description  CMOS High Voltage Logic
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Maker  SS [Silicon Supplies]
Homepage  https://siliconsupplies.com/
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 CMOS High Voltage Logic – CD4070B
 
 
 
 
 
 
CMOS Quad 2-Input Exclusive-OR gate in bare die form
High Input Voltage up to 20V
Symmetrical Output Characteristics
Max input current 1µA at 18V over full Military
Temperature Range
Low Power TTL compatible
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Die Size (Unsawn)
1524 x 1270
50 x 37
µm
mils
Minimum Bond Pad Size
102 x 102
4 x 4
µm
mils
Die Thickness
635 (±20)
25 (±0.79)
µm
mils
Top Metal Composition
Al 1%Si 1.1µm
Back Metal Composition
N/A – Bare Si
Specified at 5V, 10V & 15V
Direct drop-in replacement for obsolete
components in long term programs.  
Rev 1.0
19/09/18
Features:
The following part suffixes apply:
The CD4070B provides the system designer with direct
implementation of the Exclusive-OR function. The
device has equal source and sink current capabilities
and conforms to standard B series output drive.
Device outputs are buffered which improves transfer
characteristics by providing very high gain. The device
is capable of driving x2 low power TTL loads or x1
LSTTL load. The CD4070B is primarily used for higher
voltage acceptance and where low power dissipation
and/or high noise immunity are required.
Ordering Information
Description
Die Dimensions in µm (mils)
1524 (60)
No suffix - MIL-STD-883 /2010B Visual Inspection
“H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
“K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
Supply Formats:
Mechanical Specification
Default – Die in Waffle Pack (400 per tray capacity)
Sawn Wafer on Tape – On request
Unsawn Wafer – On request
Die Thickness <> 635µm(25 Mils) – On request
Assembled into Ceramic Package – On request
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