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K6R4008V1D-TC10 Datasheet(PDF) 9 Page - Samsung semiconductor |
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K6R4008V1D-TC10 Datasheet(HTML) 9 Page - Samsung semiconductor |
9 / 12 page K6R4016C1D CMOS SRAM PRELIMPreliminaryPPPPPPPPPINARY Rev 2.0 - 9 - June 2003 NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. t CW is measured from the later of CS going low to end of write. 4. t AS is measured from the address valid to the beginning of write. 5. t WR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE , CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not . be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. Address CS Valid Data UB, LB WE Data in Data out TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LBControlled) tWC tCW(3) tBW tWP(2) tDH tDW tWR(5) tAW tAS(4) High-Z High-Z(8) tBLZ tWHZ(6) High-Z TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) Address CS tAW tDW tDH Valid Data WE Data in Data out High-Z High-Z(8) UB, LB tCW(3) tWP(2) tAS(4) tWC tWR(5) High-Z High-Z tLZ tWHZ(6) tBW |
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