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M368L3223CTL Datasheet(PDF) 5 Page - Samsung semiconductor

Part # M368L3223CTL
Description  256MB DDR SDRAM MODULE Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
Download  12 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

M368L3223CTL Datasheet(HTML) 5 Page - Samsung semiconductor

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184pin Unbuffered DDR SDRAM MODULE
Rev. 0.3 May. 2002
M368L3223CTL
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, V OUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
V DD
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to Vss
VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
P D
12
W
Short circuit current
IOS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Notes 1. Includes
± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in V REF noise. VREF should be de-coupled with an inductance of
≤ 3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Recommended operating conditions(Voltage referenced to V SS=0V, T A=0 to 70
°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V DD of 2.5V)
VDD
2.3
2.7
I/O Supply voltage
VDDQ
2.3
2.7
V
I/O Reference voltage
V REF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination voltage(system)
VTT
V REF-0.04
VREF+0.04
V
2
Input logic high voltage
V IH(DC)
VREF+0.15
VDDQ +0.3
V
4
Input logic low voltage
VIL(DC)
-0.3
V REF-0.15
V
4
Input Voltage Level, CK and CK inputs
V IN(DC)
-0.3
VDDQ +0.3
V
Input Differential Voltage, CK and CK inputs
V ID(DC)
0.3
VDDQ +0.6
V
3
Input crossing point voltage, CK and CK inputs
VIX(DC)
1.15
1.35
V
5
Input leakage current
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver)
;V OUT = VTT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver)
;V OUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver)
;V OUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver)
;V OUT = VTT - 0.45V
IOL
9
mA


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