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M368L3223CTL-LA2 Datasheet(PDF) 8 Page - Samsung semiconductor |
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M368L3223CTL-LA2 Datasheet(HTML) 8 Page - Samsung semiconductor |
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8 / 12 page  184pin Unbuffered DDR SDRAM MODULE Rev. 0.3 May. 2002 M368L3223CTL AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component) Parameter Symbol -TCB3 (DDR333) -TCA2 (DDR266A) -TCB0 (DDR266B) Unit Note Min Max Min Max Min Max Row cycle time tRC 60 65 65 ns Refresh row cycle time tRFC 72 75 75 ns Row active time tRAS 42 70K 45 120K 45 120K ns RAS to CAS delay tRCD 18 20 20 ns Row precharge time tRP 18 20 20 ns Row active to Row active delay tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns Last data in to Read command tWTR 1 1 1 tCK Col. address to Col. address delay tCCD 1 1 1 tCK Clock cycle time CL=2.0 tCK 7.5 12 7.5 12 10 12 ns 5 CL=2.5 6 12 7.5 12 7.5 12 ns 5 Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS-out access time from CK/CK tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/ CK tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - 0.45 - 0.5 - 0.5 ns 5 Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns 2 DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 0.9 1.1 tCK Address and Control Input setup time(fast) tIS 0.75 0.9 0.9 ns 6 Address and Control Input hold time(fast) tIH 0.75 0.9 0.9 ns 6 Address and Control Input setup time(slow) tIS 0.8 1.0 1.0 ns 6 Address and Control Input hold time(slow) tIH 0.8 1.0 1.0 ns 6 Data-out high impedence time from CK/ CK tHZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data-out low impedence time from CK/ CK tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Input Slew Rate(for input only pins) tSL(I) 0.5 0.5 0.5 V/ns 6 Input Slew Rate(for I/O pins) tSL(IO) 0.5 0.5 0.5 V/ns 7 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 V/ns 10 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 |
Similar Part No. - M368L3223CTL-LA2 |
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Similar Description - M368L3223CTL-LA2 |
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