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ZL50018 Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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ZL50018 Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 136 page  ZL50018 Data Sheet 10 Zarlink Semiconductor Inc. Changes Summary The following table captures the changes from the October 2004 issue. Page Item Change 39, 76, 77 Section 12.1, “DPLL Timing Modes“ on page 39 RCCR Register bits “FDM1 - 0” on page 76 RCSR Register bits “DPM1 - 0” on page 77 • The on-chip DPLL’s normal, holdover, automatic, and freerun modes are now collectively referred to as DPLL timing modes instead of operation modes. This change is to avoid confusion with the two main device operating modes; the master and slave modes. 39, 40 Section 12.1.3.1, “Automatic Reference Switching Without Preferences“ on page 39 and Section 12.1.3.2, “Automatic Reference Switching With Preference“ on page 40 • Section 12.1.3.1 and Section 12.1.3.2 added to clarify the DPLL’s automatic reference switching with and without preference operations in Automatic Timing Mode. 42, 45 Section 12.1.4, “Freerun Mode“ on page 42, and Section 15.4, “Fast Locking Mode“ on page 45 • Added description to specify that the device should not be in freerun and fast lock modes simultaneously. This is important in order to avoid incorrect output frame pulse generation. 72 Table 36, Lock Detector Threshold Register (LDTR) Bits • Clarified threshold calculations. 74 Table 39, “Bandwidth Control Register (BWCR) Bits” Note 3. • Added a table footnote to specify that the DPLL’s fastlock and freerun modes should not be set simultaneously. 75 Table 40, “Reference Change Control Register (RCCR) Bits” Bits “PRS1 - 0“ and Bits “PMS2 - 0“ • Added description to clarify that only two consecutive references can be used in automatic timing mode with a preferred reference. 76 Table 40, “Reference Change Control Register (RCCR) Bits”, Bits “FDM1 - 0“ • Added description to specify the device should not be in freerun and fast lock modes simultaneously. |
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