AIC811/AIC812

BLOCK DIAGRAM

6

20K

R2

R1

MR

GND

RESET

(RESET)

Reset Generator

-

+

Bandgap

VCC

PIN DESCRIPTIONS

GND Pin

:

Ground.

threshold.

RESET Pin (AIC812) :

Active high output pin. RESET output remains high while Vcc below reset

threshold.

:

Logic low manual reset input. This active-low input has an internal 20k

Ω pull-up

resistor. It can be driven by a TTL or CMOS, or shorted to ground with a switch.

Leave open when unused.

Vcc Pin

:

Supply voltage.

DETAILED DESCRIPTIONS OF TECHNICAL TERMS

If a brownout condition occurs (VCC drops below

VCC goes below the reset threshold, the internal

internal timer is activated after VCC returns

low for the reset timeout period.

RESET OUTPUT

μ

P will be activated at a valid reset state. These

μ

P supervisory circuits assert reset to prevent

code

execution

errors

during

power-up,

power-down, or brownout conditions.

for the reset timeout period; after this interval,

reset. AIC812 has an active-high RESET output