TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET

TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD

FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS

SGLS165 – APRIL 2003

5

POST OFFICE BOX 655303

TPS752xx RESET timing diagram

VI

Vres

(see Note A)

Vres

t

t

t

VO

Threshold

Voltage

RESET

Output

100 ms

Delay

100 ms

Delay

Output

Undefined

Output

Undefined

VIT +(see Note B)

VIT –(see Note B)

VIT –(see Note B)

VIT +(see Note B)

Less than 5% of the

output voltage

NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.